1. Field of the Invention
The present invention relates, in general, to integrated circuits and, more particularly, to multilayer or three-dimensional integrated circuits and fabrication methods therefor.
2. Description of the Art
Integrated circuits are typically fabricated from semiconductor wafers cut from a large crystal. The semiconductor wafers are generally from 200 .mu.m to 400 .mu.m thick and are of uniform crystalline material. The actual integrated circuit is formed on the top surface of the wafer by various doping, oxide, metal deposition and etching processes. Since this provides a basic two-dimensional structure, the overall density of such integrated circuits per given area is limited.
In an effort to overcome this density limit and to produce devices having greater densities, it has been proposed to form semiconductor devices using multiple layers of integrated circuitry. The greatest obstacle in the production of multiple layers of integrated circuits is the solid semiconductor crystalline wafer. Vertical conductive paths are required for multiple layer construction. A solid wafer is not directly usable without expensive and time consuming processing methods used to produce the required vertical conductive paths.
Many ways of forming such multiple layer, integrated circuit devices are known, the most common of which is through the use of alternating layers of insulating material and semiconductive material applied to the semiconductive wafer through various deposition processes, such as chemical vapor deposition or molecular beam epitaxy. Through these processes, multiple layers may be formed with circuits integrated in each semiconductor layer. The main drawback of these processes is that as multiple layers of integrated circuits are formed, the number of defective devices increases. In the basic two-dimensional integrated circuit, each integrated circuit formed on a wafer is tested and the defective circuits discarded. However, in multiple layer integrated circuit devices, as the number of layers increases, a point will be reached at which the number of usable devices approaches zero.
Thus, it would be desirable to provide a semiconductor wafer that could include the vertical conductive paths where required for multiple layer applications. It would also be desirable to provide a semiconductor wafer which has a very thin but mechanically stable structure. It would also be desirable to provide a semiconductor wafer, suitable for multiple layer applications, that can be used with conventional, existing processing techniques and equipment. It would be desirable to provide an integrated circuit having thin layers of semiconductive material constructed in such a manner so as to duplicate the vertical conductive paths used in multiple layer integrated circuit devices as well as the multiple layer surfaces for circuit integration. It would also be desirable to provide a multiple layer integrated circuit device which can be made according to a fabrication process which increases the yield of usable individual integrated circuits. It would also be desirable to provide a multiple layer integrated circuit device which can be constructed using conventional, existing processing techniques and equipment.